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Digital Verification Engineer

Posted on December 29, 2020

Description and Responsibilities:

Peraso is actively seeking intermediate and experienced Digital Verification engineers to support the development of a new next-generation mmWave chipset. The successful candidate will have recent experience verifying complex SoC systems using industry-standard tools including constrained-random, directed and coverage-driven verification.

  • Test bench and verification IP development such as drivers and monitors
  • Test plan development and execution
  • Test development, debugging and coverage closure
  • System-level test plan development and execution
  • Inter-chip verification and co-simulation
  • Chip bring-up and validation support
  • Verification support for ATE functional vector generation
  • C API development for low-level hardware and peripherals
  • Verification process and methodology evaluations and improvements
  • Regression analysis

Qualifications:

Requirements:

  • Sc. in Electrical/Computer Engineering or related field. M.Sc. preferred.
  • 3+ years of experience in digital verification
  • Working knowledge of SystemVerilog, C
  • Experience using assertions and managing coverage
  • Experience with GNU/Linux tools and Tcl, Perl, or other scripting languages

Preferred:

  • Knowledge of CPU architecture and SoC peripherals
  • Experience with verification of low-power and/or power-gated designs
  • Matlab & C++ experience
  • UVM experience
  • Mixed signal verification experience

We need our engineers to be versatile and passionate with an ability to tackle new problems as we continue to push technology limits.

We thank all candidates for their interest, but only those who are considered for an interview will be contacted.

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