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Digital Validation Engineer

Posted on December 29, 2020

Description and Responsibilities:

Peraso is actively seeking intermediate and experienced Digital Validation engineers to support the development of new next-generation mmWave chipset. The successful candidate will have recent experience verifying and validating complex SOCs. The candidate needs to be strong in developing low-level C/C++ applications with real time embedded coding experience, have recent experience in verifying SoC systems pre-silicon, as well as chip bringup post-silicon. This role is responsible for validating digital features of SoC processors, peripherals, and integrated systems. The candidate will take the lead software development role within the digital hardware team. This role requires a candidate able automate testing, visualize results creatively, deliver validation code, deliver product screens and support functional test program development.

  • Validation Environment/Automation development and support for ASIC and FPGA
  • System performance testing
  • Early host driver support for host interface validation and verification
  • Various stack development or integration
  • FPGA software development support
  • System power analysis
  • C/C++ methodology for validation and guidance for verification with objective of maximum sharing
  • Analog component calibration integration
  • Test bench and verification IP development
  • Test plan development and execution
  • Validation support for ATE vector generation
  • Verification pre-silicon and chip bringup post-silicon

Qualifications:

Requirements:

  • Sc. in Electrical/Computer Engineering or related field. M.Sc. preferred.
  • 3+ years of experience in validation and chip bringup.
  • 3+ years of experience in C/C++.
  • Verilog and verification experience.
  • Experience with GNU/Linux tools and Tcl, Perl, or other scripting languages
  • Experience with test automation on Windows.

Preferred:

  • Knowledge of CPU architecture and SoC peripherals.
  • Matlab experience
  • SystemVerilog or UVM experience

We need our engineers to be versatile and passionate with an ability to tackle new problems as we continue to push technology limits.

We thank all candidates for their interest, but only those who are considered for an interview will be contacted.

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